Embodiments of the present invention relate to a parallel test device and method, and more particularly to a technology for performing a multi-bit parallel test by compressing data.
In recent times, a semiconductor memory device includes a read global bus and a write global bus, instead of one global bus, such that it improves a slope of global input/output (I/O) signals. The write global bus transmits data received from data pads to a cell array during data recording. In addition, the read global bus transmits data received from a cell array to a data pad during data reading.
As semiconductor memory devices are highly integrated in proportion to rapid development of fabrication technologies, the semiconductor memory devices have been manufactured and then tested using a high-priced test device for a long period of time so as to guarantee reliability of chips contained in the semiconductor memory devices. In order to test the semiconductor memory devices, a self-test circuit is embedded into chips in a process of manufacture so as to reduce time and costs consumed in the self-testing process.
In order to reduce costs requisite for a test device configured to test and verify characteristics and functions of semiconductor chips, as many semiconductor chips as possible must be tested by only one testing. In order to test a large number of semiconductor chips through a channel allocated to each device, there is a need to test all the memory chips using as less chips as possible.
A conventional parallel test device serving as a self-testing device determines the presence or absence of a passed/failed state on the basis of a bank associated with the principal defective cells of semiconductor chips. However, the conventional parallel test device has been configured to copy I/O line data used for I/O lines contained in a specific part unused when all the cells are tested using a small number of I/O lines.
That is, the same data is written into a plurality of I/O lines using a single I/O line during the I/O data compression mode. However, it is impossible for the conventional parallel test device to recognize the presence or absence of one or more defective parts generated until I/O line data used for I/O lines unused in the write operation is copied. In addition, the conventional parallel test device is configured to use test global I/O lines during the read operation, such that it is impossible for the conventional parallel test device to recognize the presence or absence of a defective part in a normal global I/O line.
That is, it is impossible for the conventional parallel test device to screen the presence or absence of a defective part of a normal path unused in the multi-bit parallel test mode. In addition, the conventional parallel test device is unable to recognize the presence or absence of a defective part in a peripheral circuit during a normal mode instead of a test mode.
As described above, assuming that a defective part generated in the peripheral circuit is not recognized and a subsequent process is continuously performed, the loss of costs caused by this unnecessary subsequent process unavoidably increases. Specifically, when a multi-chip combined with other chips is implemented, a failure of the entire multi-chip occurs, such that the scope of damage of the multi-chip is unavoidably extended.
In other words, since one defective chip occurs in a package step after completion of the multi-bit parallel test on a wafer, Multi Chip Package (MCP), Double Die Package (DDP), and Quad Die Package (QDP), each of which is composed of a plurality of stacked chips, are failed because of the defective chip, resulting in increase in the loss of time and costs.